This reverts commit 14b3fb2.

This reverts commit 761e9c6.

…s for SG2044"

This reverts commit 7fd8539.

This reverts commit 1361f63.

This reverts commit 666e16e.

This reverts commit e35a219.

…g affinity"

This reverts commit f8237b9.

This reverts commit 855ac46.

…s_mmap"

This reverts commit f2f09f1.

This reverts commit ba538ba.

This reverts commit d0253a4.

This reverts commit 6060c57.

This reverts commit cc98996.

The variable type of offset should be consistent with the relevant
interfaces of mmap which described in commit 295f100 ("syscalls:
mmap(): use unsigned offset type consistently"). Otherwise, a user input
with the top bit set would result in a negative page offset rather than a
large one.

Signed-off-by: Jessica Liu <[email protected]>
Tested-by: Han Gao <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: hand-applied mangled patch; fixed checkpatch error]
Signed-off-by: Paul Walmsley <[email protected]>
(cherry picked from commit 316b60b)
Signed-off-by: Han Gao <[email protected]>

Compared with IO attributes, NC attributes can improve performance,
specifically in these aspects: Relaxed Order, Gathering, Supports Read
Speculation, Supports Unaligned Access.

Signed-off-by: Yunhui Cui <[email protected]>
Signed-off-by: Qingfang Deng <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
(cherry picked from commit 3a8ee3a)
Signed-off-by: Han Gao <[email protected]>

plic_set_affinity() always calls plic_irq_enable(), which clears up the
priority setting even the interrupt is only masked. This unmasks the
interrupt unexpectly.

Replace the plic_irq_enable/disable() with plic_irq_toggle() to avoid
changing the priority setting.

Suggested-by: Thomas Gleixner <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Nam Cao <[email protected]> # VisionFive 2
Tested-by: Chen Wang <[email protected]> # Pioneerbox
Reviewed-by: Nam Cao <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Link: https://lore.kernel.org/lkml/[email protected]/
(cherry picked from commit adecf78)
Signed-off-by: Han Gao <[email protected]>

As the MSI controller on SG2044 uses PLIC as the underlying interrupt
controller, it needs to call irq_enable() and irq_disable() to
startup/shutdown interrupts. Otherwise, the MSI interrupt can not be
startup correctly and will not respond any incoming interrupt.

Introduce irq_chip_startup_parent() and irq_chip_shutdown_parent() to allow
the interrupt controller to call the irq_startup()/irq_shutdown() callbacks
of the parent interrupt chip.

In case the irq_startup()/irq_shutdown() callbacks are not implemented for
the parent interrupt chip, this will fallback to irq_chip_enable_parent()
or irq_chip_disable_parent().

Suggested-by: Thomas Gleixner <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Chen Wang <[email protected]> # Pioneerbox
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Link: https://lore.kernel.org/lkml/[email protected]/
(cherry picked from commit 7a721a2)
Signed-off-by: Han Gao <[email protected]>

As the RISC-V PLIC cannot apply affinity settings without invoking
irq_enable(), it will make the interrupt unavailble when used as an
underlying interrupt chip for the MSI controller.

Implement the irq_startup() and irq_shutdown() callbacks for the PCI MSI
and MSI-X templates.

For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, the parent startup
and shutdown functions are invoked. That allows the interrupt on the parent
chip to be enabled if the interrupt has not been enabled during
allocation. This is necessary for MSI controllers which use PLIC as
underlying parent interrupt chip.

Suggested-by: Thomas Gleixner <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Chen Wang <[email protected]> # Pioneerbox
Reviewed-by: Chen Wang <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Link: https://lore.kernel.org/all/[email protected]

(cherry picked from commit 54f45a3)
Signed-off-by: Han Gao <[email protected]>

When using NVME on SG2044, the NVME drvier always complains about "I/O tag
XXX (XXX) QID XX timeout, completion polled", which is caused by the broken
affinity setting mechanism of the sg2042-msi driver.

The PLIC driver can only the set the affinity when enabled, but the
sg2042-msi driver invokes the affinity setter in disabled state, which
causes the change to be lost.

Cure this by implementing the irq_startup()/shutdown() callbacks, which
allow to startup (enabled) the underlying PLIC first.

Fixes: e96b93a ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller")
Reported-by: Han Gao <[email protected]>
Suggested-by: Thomas Gleixner <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Chen Wang <[email protected]> # Pioneerbox
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/all/[email protected]

(cherry picked from commit 9d8c418)
Signed-off-by: Han Gao <[email protected]>

…2044

The MSI controller on SG2044 has the ability to allocate multiple PCI MSI
interrupts. So the PCIe controller driver can use this feature if the
hardware supports multiple PCI MSI interrupts.

Add the MSI_FLAG_MULTI_PCI_MSI flag to the supported_flags of SG2044
msi_parent_ops to enable this functionality.

Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Chen Wang <[email protected]> # Pioneerbox
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/all/[email protected]

(cherry picked from commit 7ee4a5a)
Signed-off-by: Han Gao <[email protected]>

…p|shutdown]_parent()

For MSI controllers which only support MSI_FLAG_PCI_MSI_MASK_PARENT, the
newly added callback irq_startup() and irq_shutdown() for
pci_msi[x]_template will not unmask or mask the interrupt when startup()
resp.  shutdown() is invoked. This prevents the interrupt from being
enabled resp. disabled.

Invoke irq_[un]mask_parent() in cond_[startup|shutdown]_parent(), when the
interrupt has the MSI_FLAG_PCI_MSI_MASK_PARENT flag set.

Fixes: 54f45a3 ("PCI/MSI: Add startup/shutdown for per device domains")
Reported-by: Linux Kernel Functional Testing <[email protected]>
Reported-by: Nathan Chancellor <[email protected]>
Reported-by: Wei Fang <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Nathan Chancellor <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Tested-by: Jon Hunter <[email protected]>
Tested-by: Wei Fang <[email protected]>
Tested-by: Chen Wang <[email protected]> # Pioneerbox/SG2042
Acked-by: Bjorn Helgaas <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Closes: https://lore.kernel.org/regressions/aK4O7Hl8NCVEMznB@monster/
Closes: https://lore.kernel.org/regressions/20250826220959.GA4119563@ax162/
Closes: https://lore.kernel.org/all/[email protected]/
(cherry picked from commit 727e914)
Signed-off-by: Han Gao <[email protected]>

Move vendor errata definitions into errata_list_vendors.h.

Signed-off-by: Guo Ren (Alibaba DAMO Academy) <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Tested-by: Han Gao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: updated to apply and to make the whitespace consistent]
Signed-off-by: Paul Walmsley <[email protected]>
(cherry picked from commit 16d18e3)
Signed-off-by: Han Gao <[email protected]>

According to the description of [1], sg2042 is divided into 4 numa.
STREAM test performance will improve.

Before:
Function    Best Rate MB/s  Avg time     Min time     Max time
Copy:           10739.7     0.015687     0.014898     0.016385
Scale:          10865.9     0.015628     0.014725     0.016757
Add:            10622.3     0.023276     0.022594     0.023899
Triad:          10583.4     0.023653     0.022677     0.024761

After:
Function    Best Rate MB/s  Avg time     Min time     Max time
Copy:           34254.9     0.005142     0.004671     0.005995
Scale:          37735.5     0.004752     0.004240     0.005407
Add:            44206.8     0.005983     0.005429     0.006461
Triad:          43040.6     0.006320     0.005576     0.006996

[1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png

Signed-off-by: Han Gao <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
(cherry picked from commit 4d94abd)
Signed-off-by: Han Gao <[email protected]>

Add binding for Sophgo SG2042 PCIe host controller.

Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Link: https://patch.msgid.link/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com
(cherry picked from commit 4e4a4f5)
Signed-off-by: Han Gao <[email protected]>

…ore using it

cdns_pcie::ops might not be populated by all the Cadence glue drivers. This
is going to be true for the upcoming Sophgo platform which doesn't set the
ops.

Hence, add a check to prevent NULL pointer dereference.

Signed-off-by: Chen Wang <[email protected]>
[mani: reworded subject and description]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Link: https://patch.msgid.link/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com
(cherry picked from commit 49a6c16)
Signed-off-by: Han Gao <[email protected]>

Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses
the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe
controller in SG2042 works in host mode only, supporting data rate up to 16
GT/s and lanes up to x16 or x8.

Signed-off-by: Chen Wang <[email protected]>
[mani: reworded description and minor code cleanups]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
(cherry picked from commit 1c72774)
Signed-off-by: Han Gao <[email protected]>

Change the return value of match_noXlvl() to return the SATP mode that
will be used, rather than the mode being disabled. This enables unified
logic for return value judgement with the function that obtains mmu-type
from the fdt, avoiding extra conversion. This only changes the naming,
with no functional impact.

Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
(cherry picked from commit f3243be)
Signed-off-by: Han Gao <[email protected]>

Some RISC-V implementations may hang when attempting to write an
unsupported SATP mode, even though the latest RISC-V specification
states such writes should have no effect. To avoid this issue, the
logic for selecting SATP mode has been refined:

The kernel now determines the SATP mode limit by taking the minimum of
the value specified by the kernel command line (noXlvl) and the
"mmu-type" property in the device tree (FDT). If only one is specified,
use that.
- If the resulting limit is sv48 or higher, the kernel will probe SATP
  modes from this limit downward until a supported mode is found.
- If the limit is sv39, the kernel will directly use sv39 without
  probing.

This ensures SATP mode selection is safe and compatible with both
hardware and user configuration, minimizing the risk of hangs.

Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
(cherry picked from commit 17e9521)
Signed-off-by: Han Gao <[email protected]>

The early version of XuanTie C910 core has a store merge buffer
delay problem. The store merge buffer could improve the store queue
performance by merging multi-store requests, but when there are not
continued store requests, the prior single store request would be
waiting in the store queue for a long time. That would cause
significant problems for communication between multi-cores. This
problem was found on sg2042 & th1520 platforms with the qspinlock
lock torture test.

So appending a fence w.o could immediately flush the store merge
buffer and let other cores see the write result.

This will apply the WRITE_ONCE errata to handle the non-standard
behavior via appending a fence w.o instruction for WRITE_ONCE().

This problem is only observed on the sg2042 hardware platform by
running the lock_torture test program for half an hour. The problem
was not found in the user space application, because interrupt can
break the livelock.

Reviewed-by: Leonardo Bras <[email protected]>
Signed-off-by: Guo Ren (Alibaba DAMO Academy) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>